In a conventional microcomputer system, in order to reduce power consumption, a microcomputer is shifted to a sleep mode that stops the supply of operation clock to hold the internal state when the microcomputer becomes a state in which an event to be processed does not occur. For example, U.S. Pat. No. 5,737,588 (JP 8-76873A) discloses that the operation of a main oscillator circuit that supplies a clock signal to a central processing unit (CPU) is controlled by hardware logic that operates in response to a CR oscillation signal that is lower in frequency than the clock signal. That is, when the microcomputer is shifted to the sleep mode, the CR oscillation signals are counted up by a timer, and the main oscillator circuit restarts after a given period of time elapses to wake up the microcomputer.
As a result of increasingly reducing the size of the microcomputer, a leak current is generated more in a circuit to which a power is supplied. For this reason, even if only the supply of the clock signal to the CPU stops, it is difficult to reduce the power consumption because of the leak current (off leak). Under the circumstances, it is proposed to block power supply as much as possible to reduce the power consumption when it is unnecessary to operate the microcomputer.
In order to block the power that is supplied to the microcomputer to reduce the power consumption, there is required a configuration in which the power is supplied to the microcomputer at appropriate timing to restart the microcomputer. However, when the above function is configured by the hardware logic as in U.S. Pat. No. 5,737,588, the power supply turns on to start the microcomputer after a given period of time has elapsed, resulting in that the effect of reducing the power consumption is lowered.